Current Research Projects

The CDL conducts fundamental research in Electromagnetic Compatibility which includes emission, immunity, and ESD to develop robust electronic systems. The main areas of application are automotive power converters, smart power devices, detection and analysis of damaging electrostatic discharge and RF and antenna frontends of mobile devices. The research challenges worked on are the development of physical models and therefrom training of machine learning (ML) models. Other ML models will be constructed from measurements. The ML models will be used for parameter studies, risk analysis, optimization, and model calibration.

The goal of the project is to combine electromagnetic full-wave simulation with high-voltage corona and spark simulation. This multi-physics approach will be verified by sets of experiments that vary critical parameters along the parameter ranges covered by electrostatic discharges and corona discharges along dielectric surfaces with and without metal backing.

Investigation of ESD partial discharge processes on plastic housings of micromechanical sensor devices.

The main focus of the work is on the lifetime evaluation of two-dimensional, resonant microelectromechanical mirrors.

Definition of simulation scopes and assessment of simulation results. Development and definition of simulative and metrological methods for the evaluation of the EMC development status.

The one contact harmonic test system is being tested in this project.

This SOW applies to University’s research services on ESD Threat Assessment; Improving methods and simulations for quality testing beyond regulatory requirements; SEED Analysis; and Quantifying and reproducing the rock tumbler as an ESD source.

Wide bandgap semiconductor devices allow the design of power electronic systems with much high switching frequencies than silicon power semiconductors. This risen switching frequency brings up new challenges in mastering electromagnetic compatibility (EMC) in the design. To lower design costs and shorten time to markets, it is beneficial to pre-estimate EMC in simulation and co-simulation. The goal is the development of novel and optimized methods for modeling and simulation electromagetic interference (EMI) of electronic based systems (EBS) based on a power electronic hardware demonstrator.

Existing devices will be measured to find important device parameters which influence HD. If needed, a combination of devices inside a more complex electronic circuit will be investigated as well. The continuous operation as well as a burst mode will be investigated. The burst mode is important as devices seem to behave differently during the first oscillations of the high frequency signal. If promising for understanding the root causes, the phase of the harmonics will also be captured. The measurement may include DC bias, temperature variation, digital data traffic to reflect usage scenarios.

Ionizing radiation, like X- and gamma rays, cause a gradual damage in semiconductor devices. Radiationinduced defects build up throughout the exposure time leading to change of transistor characteristics. This leads to reliability issues in integrated circuits (IC). Over the years scaling of the integrated circuit process improved the robustness to radiation thanks to thinner silicon oxides under MOS transistor gate and higher bulk doping levels. However, starting with 40 nm and 28 nm process nodes to reduce high gate leakage currents the gate material had to change to one with high-dielectric constant. This new gate stack in combination with aggressive scaling is expected to uncover new radiation effects. The project SIRENS will focus on these modern process nodes and examine device-level effects and mechanisms of defects forming due to X-rays. Custom integrated test circuits in 40 nm and 28 nm processes will be designed. These will include dedicated test structures, above all arrays of different size and type transistors. Test structures will be exposed to X-ray radiation to characterize parameters drift. Also energy and spatial distributions of traps in the new gate stack will be studied. The effects will be examined from three perspectives. First, the transistor geometry ependence will be examined. The reason of the apparent lack of radiation induced narrow channel effect in p-channel MOS transistor will be investigated. The radiation-induced short channel effect will be examined to determine the dominating effect amongst the three hypotheses: of charge trapping in sidewall spacer, of halo implant increasing the effective doping, and of gate extension area influencing the electric field. The second perspective covers examination of the extent of possible radiation damage. For this, the evolution of traps density will be evaluated up to very high total ionizing dose levels, reaching 1 Grad, including annealing. The final third aspect is studies of dose rate sensitivity of MOS transistors. The hypothesis, suggested in several recent papers, states that high dose rate in accelerated X-ray testing could lead to illusionary lower damage effects than the stress with low dose rate. Today’s understanding of radiation effects in scaled devices down to 28 nm process is only superficial. The proposed studies encompassing two process nodes (40 nm and 28 nm) and three foundries (Fab40, Fab28- A and Fab28-B) will greatly enrich the state of the current knowledge.