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Integrated Systems Technology

Course developed by: Mario Casu, (POLITO) Polytechnic University of Turin
Contact: mario.casunoSpam@polito.it

Course Description

The course is mainly focused on technologies for scalable and heterogeneous integrated functionalities. Future breakthroughs require the study of new devices as well new materials and integration schemes: the knowledge of the relationships between technological processes, device structures and system performance is mandatory for electronic designers. The scaling for planar CMOS technologies during last years can be considered a successful example of the advancement of the technological processes that made possible the definition of 3D devices.In this scenario, the Integrated Systems Technology course will provide the skills enabling the student to understand the relations between physical models at the technological level, and the system level performance.
The course will provide a wide range of technological competences, exploited in the practice classes to guarantee a sound quantitative comprehension, and in the simulation laboratories to allow a correct interpretation at the system level of the possible technological solutions.

Learning Objectives

  • Classification of the most relevant CMOS fabrication processes in accordance to ITRS roadmap and their evaluation in terms of figures of merit (Ion, Ioff, intrinsic time....) 
  • Evaluation of consequences due to the scaling techniques used in integration processes both on the single devices and on the inteconnects among structures. 
  • Knowledge of the main fabrication technologies for nanometer scale devices: advanced gate and channel technologies. 
  • Knowledge of adavanced CMOS processes as SOI, Double gate, FinFET, GAA. 
  • Knowlege of the inteconnections and packaging technologies and evaluation of their electrical behavior in term of delays, crosstlak, IR drop. 
  • Knowlege of the heterogenous and 3D integration technologies.
  • Ability of using simulation tools for the estimation of the consequences on device and system of the technological parameters. 
  • Knowledge of the emerging technologies that can be considered a possible replacement of CMOS processes.

 

Link & Infos
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Course access (via PoLiTo)
Open access provided? No
Course duration: ~ 60 hours
Course type: e-learning
Target audience: Students at Master’s level
Course language: English
Is this course free? No
Self-paced course? Yes
Is the certificate / are the credentials free? No
Assessment type: In-class exam
Course/Training effort: 6 ECTS