Latch-Up Detection and Prediction in Reconfigurable Logic

FPGAs have a considerable advantage compared to ASICs – they are reconfigurable.Thus, hardware can be modified in the field without physical access to the device.This feature makes these devices attractive for space applications like satellites. However, the harsh environment in outer space comes with significant challenges, such as partial or full latch-ups in the implemented logic caused by cosmic radiation.While specialized radiation-hard FPGAs exist, they have a significantly increased cost point. Hence, a question arises: Can we circumvent specialized hardware by reliably detecting and predicting emerging latch-up effects by in-chip sensors in a redundant system? You will find out when conducting this master's thesis in collaboration with Fraunhofer EMI.

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Student Target Groups:

  • Information and Computer Engineering (ICE)
  • Computer Science (CS)
  • Electrical Engineering (EE)

Thesis Type:

  • Master Thesis / Master‘s Project

Goal and Tasks:

  • Understand internal FPGA technology and related semiconductor physics
  • Create a fault model for latch-ups
  • Extend your solution to trace and predict latchups

Recommended Prior Knowledge:

  • Digital Design
  • FPGAs
  • Electronics


  • a.s.a.p.