Dynamic Partial Reconfiguration (DPR) enables on- demand specialization of embedded RISC–V cores by swapping accelerator logic at runtime while the CPU keeps running. This thesis studies how DPR im- proves flexibility, performance, and energy efficiency in FPGA/eFPGA-based systems. You will design a stan- dardized socket between the static pipeline and recon- figurable regions using instruction-set extension inter- faces (custom instructions/CSRs), and prototype swap- pable accelerators for a dedicated usecase (e.g., crypto, DSP). The work spans hardware, software, and tool flow: partial bitstreams, reconfiguration control, and driver/runtime integration.
Download as PDF
Student Target Groups:
- Computer Science (CS)
- Information and Computer Engineering (ICE)
- Electrical Engineering (EE)
- Space Sciences and Earth from Space (SSES)
Thesis Type:
- Master Thesis / Master Project / Bachelor Thesis
Goal and Tasks:
- Specify a standardized extension interface between the static and DPR regions.
- Prototype your CPU system in an FPGA.
- Implement DPR functionality.
- Evaluate performance/energy/area/latency vs. static designs; provide open, reproducible artifacts.
Recommended Prior Knowledge:
- FPGA design, ideally with DPR concepts
- Processor architecture, preferably RISC–V
- Verilog/SystemVerilog
Start:
Contact: