Greyhound is an open-source RISC-V SoC that tightly couples an embedded FPGA (eFPGA) fabric and was built entirely using open-source frameworks (the FAB- ulous eFPGA generator and OpenLane/LibreLane ASIC flow). It demonstrates how on-chip reconfigurable logic can serve as a custom instruction extension or a flexi- ble peripheral for the processor. Building on this base- line, this thesis will explore a next-generation eFPGA- enabled SoC in the open-source silicon ecosystem. Pos- sible directions include improved CPU–FPGA inter- faces, tighter integration of the eFPGA fabric with the SoC, and physical design optimizations for timing clo- sure and power efficiency. The focus is on using open- source tools and flows to ensure reproducible chip gen- eration, with an aim for publishable results.
Download as PDF
Student Target Groups:
- Computer Science (CS)
- Information and Computer Engineering (ICE)
- Electrical Engineering (EE)
Thesis Type:
- Master Thesis / Master Project
Goal and Tasks:
- Extend the Greyhound SoC or design a new RISC-V + eFPGA SoC using the FABulous framework.
- Implement improved custom instruction or periph- eral interfaces for the eFPGA.
- Achieve tighter integration between the eFPGA fab- ric and SoC subsystems.
- Optimize the eFPGA tile layout and SoC floorplan.
- Explore advanced open-source ASIC flows and eFPGA architecture enhancements (new standard cells, OpenROAD/LibreLane improvements, adding BRAM/DSP tiles) to improve performance and repro- ducibility.
Recommended Prior Knowledge:
- Digital design (Verilog/SystemVerilog)
- Processor architecture (RISC-V, SoC integration)
- FPGA/eFPGA fundamentals
- Basic ASIC design flow (e.g., OpenLane/OpenROAD)
Start:
Contact: