This thesis explores the use of generative AI code assis- tants (LLM copilots) to streamline digital hardware de- sign (RTL/FPGA/ASIC) workflows. By leveraging open- source code generation models adapted specifically to hardware description languages, developers can auto- mate and improve tasks such as Verilog module genera- tion, linting, and design documentation. This thesis will explore setting up a self-hosted AI copilot environment, fine-tune the model on domain-specific data, and inte- grate it into the hardware development pipeline. Finally, the effectiveness of the AI copilot must be evaluated in terms of productivity gains and design correctness.
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Student Target Groups:
- Computer Science (CS)
- Information and Computer Engineering (ICE)
- Electrical Engineering (EE)
Thesis Type:
- Master Thesis / Bachelor Thesis / Masters Project
Goal and Tasks:
- Deploy a suitable open-source code LLM in a self- hosted environment.
- Fine-tune the model on domain-specific hardware design data (HDL code and documentation).
- Integrate the AI copilot into an RTL/FPGA design workflow (e.g., as an IDE plugin or CLI tool).
- Demonstrate the copilot on tasks like Verilog genera- tion, code linting, or synthesis optimization.
- Evaluate the impact on development productivity and design correctness.
Recommended Prior Knowledge:
- Hardware Description Languages (Ver- ilog/SystemVerilog)
- Basics of Machine Learning (neural networks, lan- guage models)
- FPGA/ASIC design flow (synthesis, simulation, veri- fication)
- Programming skills (for model fine-tuning)
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