With this project, we aim to enable dynamic par- tial reconfiguration (DPR) using fully open-source tools (Yosys for synthesis and nextpnr for place-and-route). DPR allows a portion of an FPGA to be reconfigured at runtime, but this capability is largely absent in to- day’s open-source FPGA flows. This thesis will explore and extend the toolchain to support DPR on hardware platforms that have open-tool support (such as Lattice iCE40 or ECP5). Possible directions include developing methods to partition designs into static and reconfig- urable regions, creating flows for partial bitstream gen- eration, and demonstrating on-the-fly hardware recon- figuration. The focus is on using and improving open- source tools to build a reproducible DPR flow, with an aim to contribute these enhancements back to the com- munity and achieve publishable results.
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Student Target Groups:
- Computer Science (CS)
- Information and Computer Engineering (ICE)
Thesis Type:
- Master Thesis / Master Project
Goal and Tasks:
- Analyze the current state of open-source FPGA flows and identify gaps for supporting DPR.
- Design a methodology to partition FPGA designs suitable for open-source tool flows.
- Extend or script the Yosys and nextpnr toolchain to generate partial bitstreams for a target open FPGA (e.g., Lattice iCE40/ECP5).
- Demonstrate DPR on hardware by implementing a proof of concept.
- Evaluate the DPR workflow in terms of performance and reliability, and contribute docs and/or code back to the open-source community.
Recommended Prior Knowledge:
- Digital logic design (Verilog/VHDL)
- FPGA architecture and tool flow fundamentals
- Open-source FPGA tools (Yosys, nextpnr)
- Partial reconfiguration concepts
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