System-On-Chip Physical Design
Course developed by: Francesc de Borja Moll Echeto, Electronic Engineering Dept, UPC
Contact: francesc.moll@upc.edu
Course Description
The aim of this Master course is to train students in methods of design of digital CMOS integrated circuits from a high level description to a layout in an efficient way using computers so that the resulting layout satisfies topological, geometric, timing and power-consumption constraints of the design.
Specific topics covered in the course are timing constraints and analysis; synthesis - concepts and basic flow; physical implementation (place-and-route) basic flow; clock distribution and analysis; power distribution; implementation of low power techniques; and design for testability flow.
The course has an important practical content using professional EDA tools (Cadence’s physical synthesis flow).
Learning Objectives
By the end of this course, students are able to …
- Understand and apply timing and power constraints to a complex integrated circuit.
- Perform the physical implementation of a complex integrated circuit.
- Apply low power design techniques to integrated circuit design.
- Develop techniques for the design, analysis and evaluation of electronic systems in applications such as automation, aerospace, energy distribution and generation, consumer electronics, biomedicine, etc.
- Analyze, design and evaluate microelectronic integrated circuits.
- Implement advanced design techniques of microelectronic integrated circuits.
- Use state of the art computer aided design (CAD) tools for the design of integrated circuits.
Course access (restricted to UPC enrolled students only)
Open access provided? No
Course duration: ~ 125 hours
Course type: In-class course
Target audience: Students at Masters level
Course language: English
Is this course free? No
Self-paced course? No
Is the certificate / are the credentials free? No
Assessment type: Exams, laboratory assessments, presentations