Design and functional Verification based on the SystemVerilog Language
Course developed by: Juan Manuel Moreno Aróstegui, Electronic Engineering Dept, UPC
Contact: joan.manuel.moreno@upc.edu
Who is it for?
Professionals, recent graduates, or electronic engineering students involved in the design of electronic systems.
Learning Objectives
By the end of this course, students are able to …
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Master the characteristics and methodologies of Verilog and SystemVerilog for the efficient description and synthesis of digital systems, including Object-Oriented Programming (OOP) concepts.
- Analyze advanced verification methodologies for complex digital systems, including constrained random verification, code and functional coverage, and the Universal Verification Methodology (UVM).
- Understand the structure and components of a UVM-based verification environment, including testbench architecture and elements.
- Design and verify a medium-complexity digital system by applying methodologies and tools used in industrial hardware development environments.
Course access
Open access provided? No
Course duration: ~ 20 hours
Course type: In-class course
Target audience: Professionals in the sector
Course language: Spanish
Is this course free? No
Self-paced course? No
Is the certificate / are the credentials free? No
Assessment type: Final Project