ITI/Forschung/Projekte/OpenES
OpenES - Modeling and Co-simulation for Virtual Prototyping based on Architecture Models
Development of approaches for functional verification of high level use case descriptions, their corresponding SystemC TLM test-benches, and (co)-simulation with architecture or implementation models based on TLM co-simulation. (in Arbeit) In order to improve European electronics system design productivity (faster time-to-market), design quality (less design errors and less re-designs) to stay competitive, the OpenES consortium joins forces to provide missing links in system-level design and to develop common open solutions based on four pillars: - Fill gaps in design flows with new interoperable tools and/or improve existing tools/flows ensuring the semantic continuity of the design flow. - Specifically focus on integral support of both functional and extra-functional requirements from specification to verification, jointly with the use cases defined at system level. - Raise reuse capabilities from IP to HW/SW subsystem in order to eliminate integration effort by supporting reuse of pre-integrated and pre-verified subsystems. - Enhance interoperability of models and tools by upgrading and extending existing young open standards (SystemC TLM, SystemC-AMS, IP-XACT) To demonstrate the efficiency of this approach a new tool in cooperation with CISC Semiconductors is developed in this project. The aim of the tool SHARC is to design, simulate and verify safety-critical systems in the automotive area. Safety turns out to be the key issue for future vehicle development, as the complexity in the automotive area is steadily growing. Especially when systems interact with and have an effect on the physical world, so called cyber-physical systems, its not longer sufficient to test a single behavior. The whole system must be validated as early as possible in the development cycle and at any level of granularity. This is also recommended by the ISO 262626 standard for automotive E/E systems.
Mitarbeiter
Projektleiter/in an der OE
Christian Steger
Ass.Prof. Dipl.-Ing. Dr.techn.
Teilnehmer / Mitarbeiter
Markus Schuß
Dipl.-Ing. BSc
Ralph Peter Weissnegger
Dipl.-Ing. BSc
Fördergeber
  • CISC Semiconductor GmbH
  • Österreichische Forschungsförderungsgesellschaft mbH, FFG
Forschungsgebiete
  • Hardware/Software-Codesign

Ausgewählte Publikationen

2017
Buchkapitel
Ralph Peter Weissnegger, Martin Schachner, Markus Pistauer, Christian Josef Kreiner, Kay Uwe Römer and Christian Steger Generation and Verification of a Safety-Aware Virtual Prototype in the Automotive DomainGeneration and Verification of a Safety-Aware Virtual Prototype in the Automotive Domain195 Publikation in PURE anzeigen
2016
Tagungsbeitrag
Ralph Peter Weissnegger, Markus Schuß, Christian Josef Kreiner, Markus Pistauer, Kay Uwe Römer and Christian Steger Simulation-based Verification of Automotive Safety-critical Systems Based on EAST-ADL Simulation-based Verification of Automotive Safety-critical Systems Based on EAST-ADL 245 Publikation in PURE anzeigen
Ralph Peter Weissnegger, Markus Schuß, Christian Josef Kreiner, Markus Pistauer, Kay Uwe Römer and Christian Steger Automatic Testbench Generation for Simulation-based Verification of Safety- Critical Systems in UML Automatic Testbench Generation for Simulation-based Verification of Safety- Critical Systems in UML Publikation in PURE anzeigen
Ralph Peter Weissnegger, Markus Schuß, Martin Schachner, Kay Uwe Römer, Markus Pistauer and Christian Steger A Novel Simulation-based Verification Pattern for Parallel Executions in the Cloud A Novel Simulation-based Verification Pattern for Parallel Executions in the Cloud Publikation in PURE anzeigen
Ralph Peter Weissnegger, Markus Schuß, Christian Josef Kreiner, Markus Pistauer, Kay Uwe Römer and Christian Steger Seamless integrated Simulation in Design and Verification Flow for Safety-Critical Systems Seamless integrated Simulation in Design and Verification Flow for Safety-Critical Systems Publikation in PURE anzeigen
Ralph Peter Weissnegger, Markus Schuß, Christian Josef Kreiner, Kay Uwe Römer, Markus Pistauer and Christian Steger Bringing UML/MARTE to life: A Model-Based Simulation-Framework for Safety-Critical Systems Bringing UML/MARTE to life: A Model-Based Simulation-Framework for Safety-Critical Systems Publikation in PURE anzeigen
Sonstiger Beitrag
Ralph Peter Weissnegger, Markus Schuß, Martin Schachner, Kay Uwe Römer, Markus Pistauer and Christian Steger A Novel Simulation-based Verification Pattern for Parallel Executions in the Cloud Publikation in PURE anzeigen
Ralph Peter Weissnegger A Novel Simulation-based Verification Pattern for Parallel Executions in the Cloud Publikation in PURE anzeigen
2015
Tagungsbeitrag
Ralph Peter Weissnegger, Markus Pistauer, Christian Josef Kreiner, Kay Uwe Römer and Christian Steger A Novel Method for Fast Evaluation of Cyber-Physical Systems in Compliance with Functional Safety A Novel Method for Fast Evaluation of Cyber-Physical Systems in Compliance with Functional Safety 24-25 Publikation in PURE anzeigen
Ralph Peter Weissnegger, Christian Josef Kreiner, Markus Pistauer, Kay Uwe Römer and Christian Steger A Novel Design Method for Automotive Safety-Critical Systems based on UML/MARTE A Novel Design Method for Automotive Safety-Critical Systems based on UML/MARTE 177-184 Publikation in PURE anzeigen
Ralph Peter Weissnegger, Christian Josef Kreiner, Markus Pistauer, Kay Uwe Römer and Christian Steger A Novel Method to Speed-Up the Evaluation of Cyber-Physical Systems (ISO 26262) A Novel Method to Speed-Up the Evaluation of Cyber-Physical Systems (ISO 26262) 109-114 Publikation in PURE anzeigen
2014
Tagungsbeitrag
Ralph Peter Weissnegger, Christian Steger and Markus Pistauer High Level Simulation of Cyber-Physical Systems High Level Simulation of Cyber-Physical Systems 57-58 Publikation in PURE anzeigen