SIMBA - Simulation-based Requirements Testing of Power Aware SoC's
System-on-a-chip (SOC) structures integrate both hardware and software, digital and analog components on a single chip. SOCs are driven by a number of constraints of limited resources and time-to-market. The recent evolution of SOCs regarding higher functionality continuosly created new constraints and functional requirements, which have to be taken into account during design and verification on each abstraction layer. System-level-based functional verification prototypes used as executable specifications are a recently proposed approach to cope with the large number of requirements. However, these specifications are often completeley separated from the corresponding implementation on RTL. This, however, defeats the purposes of executable specifications as a verification environment for lower levels. On the other hand it is a very exhausting process to develop executable specifications to fulfil all of the specified requirements. The SIMBA project, which is a collabroation of the Technical University Graz and the University College Dublin together with CISC Semiconductors, tries to solve these issues by extending the current design methodology towards the tight integration of requirements in each design step and abstraction level.

The SIMBA project extends the current design methodology towards the tight integration of requirements in each design step and at each abstraction level.It uses existing system- and software engineering concepts and tries to apply them to the development of System-on-Chip designs. A state-of-the-art requirements engineering tool is to be used to gather SOC requirements, which are then extracted and used to generate a system-level verification platform for the given design. These testbenches are then gradually refined to lower levels to validate the (C-Code,RTL) design implementations. This ensures that the implementation satisfies the requirements, thus maintaining a linkage between the specification and implementation. Traceability and change management of requirements known from software engineering are to be supported as well as a design space exploration functionality to determine the most suitable SOC architecture, satisfying the given constraints.
The proposed design methodology is shown below. The CISC Semiconductors tool SyAD, supporting a number of different HDLs, is used as verification platform together with a power managment tool called Rheims to support the design-space exploration with focus on power-aware systems, like ad-hoc sensor networks and RFID.

Projektleiter/in an der OE
Christian Steger
Ass.Prof. Dipl.-Ing. Dr.techn.
Teilnehmer / Mitarbeiter
Christoph Kirchsteiger
Christoph Trummer
Dipl.-Ing. Bakk.techn.
  • Österreichische Forschungsförderungsgesellschaft mbH (FFG) , FFG
Externe Partner
  • University College Dublin, UCD
  • Hardware/Software-Codesign
Beginn: 31.10.2006
Ende: 30.12.2009

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