Power-Aware Smart Card Systems - POWERCARD - Methodologies for Designing Power-Aware Smart Card Systems
Smart Cards are some of the smallest computing platforms in use today. They have limited resources, but a huge number of functional requirements. The requirement for multi-application cards increases the demand for high performance and security even more. Great efforts have been taken to find methodologies for developing and implementing low-power hardware, but almost no state-of-the-art software engineering techniques are used to design and implement the software layers – if software is layered at all. Smart card operating systems (e.g. Java CardTM Technology) were designed to let smart cards benefit from the advantage of modern software engineering techniques. Applications are developed in a high level language; the resulting code is interpreted by a virtual machine. These additional layers require even more performance, requiring the use of HW/SW codesign techniques to better support software parts in hardware. This project aims to realize a HW/SW codesign methodology for designing entire smart card systems with regard to power awareness and performance.

The goal of this project is to introduce new methodologies for designing and implementing entire systems with regard to power awareness and required performance. This requires all levels of hardware and software – including operating system and application levels – to be considered in the system design. It is expected to take between 4 and 6 years until this approach fully can be used in praxis. The first steps within the next 2 years therefore are:

  • The study of existing design methodologies and extraction of required features
  • The design of special methodologies under consideration of design parameters such as power awareness, performance and overall system security
  • The implementation of a first prototype of a smart card system based on these methodologies


As a result, we expect a power efficient system, consistent system design, an increase in system security, improved maintenance and faster time-to-market.

Staff member
Project Leader
Christian Steger
Ass.Prof. Dipl.-Ing. Dr.techn.
Reinhold Weiß
Em.Univ.-Prof. Dipl.-Ing. Dr.techn.
Participant / Staff Member
Ulrich Neffe
Dipl.-Ing.
Klaus Rothbart
Dipl.-Ing.
Funding sources
  • Österreichische Forschungsförderungsgesellschaft mbH (FFG) , FFG
Research areas
  • Hardware/Software-Codesign
Start: 31.12.2002
End: 30.07.2005

Selected Publications